Different types of memory are used in electronic apparatus for various purposes. Read only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device includes a matrix of addressable memory cells arranged in columns and rows. A typical SRAM cell includes two access transistors and a flip-flop formed with two cross-coupled inverters, each inverter having a pull-down (driver) and a pull-up (load) transistor. The gates of the access transistors in each row are connected to a word line and the sources of each of the access transistors in each column are connected to either one of a bit line pair, B or B. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the SRAM cells.
Generally, to read data from a SRAM cell, a word line driver may activate a word line according to an address decoded by a row decoder and received via a signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bit line pair sending signals representing the data in the SRAM cell to a sense amplifier coupled to the bit line pair. The sense amplifier amplifies the potential difference on the bit line pair. Data from the sense amplifier is output to the external circuitry of the associated electronic apparatus optionally through a buffer. Essentially, data is written to each SRAM cell in the opposite way.
As mentioned above, to retain the data written to the matrix of SRAM cells, or memory array, each SRAM cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, wireless apparatus may be transitioned from an active mode to a standby mode of lower power consumption. As transistor size continues to diminish (e.g., 90 nm transistors), current leakage may be unacceptably high even during standby mode, requiring a transition to a still lower power consumption level, sleep mode, or data retention mode, to conserve power adequately.
Even in sleep mode, however, current leakage is a concern. The current leakage may be a combination of subthreshold leakage current, gate leakage and diode leakage current from the SRAM cell transistors. The subthreshold leakage current may be directly related to a threshold voltage of the SRAM cell transistors. Typically, an increase in the threshold voltage reduces the subthreshold leakage current. The threshold voltage may be increased by increasing a well voltage, such as an n-well voltage Vnwell, of the SRAM cell transistors. The diode leakage current may be Gate Induced Diode Leakage (GIDL) or, similarly, Gate Edge Diode Leakage (GEDL), that is a function of a voltage from a source or drain of the transistor to a back gate of the transistor. For example, the back gate, sometimes referred to as the body of the transistor, may be a substrate of the transistor for an n-channel transistor and an n-well for a p-channel transistor. In some process variations, there may be a p-well as the back gate of the n-channel transistors. In other processes, the back gate may be a conductor separated from the channel region by a dielectric. The term back gate may cover any structure in which the voltage thereof can influence the threshold voltage of a primary gate. Typically, as voltage between the source or drain and the back gate increases, the diode leakage current also increases.
Presently, to reduce current leakage during sleep mode, voltage across the SRAM cell may be reduced as limited by static noise margin (SNM) requirements and by using back gate biases as limited by diode leakage current. For example, a high operating voltage VDD supplied to the SRAM device may be lowered to reduce voltage across the SRAM cells and the n-well voltage may be increased to raise the p-channel threshold voltage Vtp. Alternatively, a low operating voltage VSS supplied to the SRAM device may be increased to reduce the voltage across the SRAM cell and also provide back bias across n-channel transistors to raise n-channel threshold voltage Vtn. As mentioned, the increased back bias incurs an increase in the diode leakage current that reduces or negates the benefit of reduced subthreshold current. Thus, a tradeoff often occurs between increasing the voltage of the well that increases the threshold voltage and reduces the subthreshold leakage current, the Ioff current, that at the same time increases the diode leakage current.
Limiting a change in voltage to either lowering VDD or raising VSS simplifies the required circuitry and reduces the risk in voltage control. With continued miniaturization of future generation transistors, however, sufficiently lowering or raising VDD or VSS, respectively, to significantly reduce gate current may result in an increase in diode current that becomes significant relative to savings in the gate current and the subthreshold current. As devices are further scaled, heavier doping is needed to control short channel effects. This heavier doping limits the subthreshold current increase with scaling but increases the diode leakage.
Accordingly, what is needed in the art is an improved low-power SRAM device that has minimum current leakage during sleep mode. More specifically, what is needed in the art is an improved SRAM device and method of operation that reduces total current leakage, including subthreshold, gate and diode currents, for new generation transistors.